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<div class="title">DAC_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div>  </div>
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<p>Digital to Analog Converter.  
</p>

<p><code>#include &lt;<a class="el" href="stm32f4xx_8h_source.html">stm32f4xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#ab40c89c59391aaa9d9a8ec011dd0907a">CR</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#a896bbb7153af0b67ad772360feaceeb4">SWTRIGR</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#ac2bb55b037b800a25852736afdd7a258">DHR12R1</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#ae9028b8bcb5118b7073165fb50fcd559">DHR12L1</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#ad0a200e12acad17a5c7d2059159ea7e1">DHR8R1</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#a804c7e15dbb587c7ea25511f6a7809f7">DHR12R2</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#a2e45f9c9d67e384187b25334ba0a3e3d">DHR12L2</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#a4c435f0e34ace4421241cd5c3ae87fc2">DHR8R2</a></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#aa710505be03a41981c35bacc7ce20746">DOR1</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#aba9fb810b0cf6cbc1280c5c63be2418b">DOR2</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html#af6aca2bbd40c0fb6df7c3aebe224a360">SR</a></td></tr>
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<hr/><h2>Field Documentation</h2>
<a class="anchor" id="ab40c89c59391aaa9d9a8ec011dd0907a"></a><!-- doxytag: member="DAC_TypeDef::CR" ref="ab40c89c59391aaa9d9a8ec011dd0907a" args="" -->
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<p>DAC control register, Address offset: 0x00 </p>

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<p>DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C </p>

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<a class="anchor" id="a2e45f9c9d67e384187b25334ba0a3e3d"></a><!-- doxytag: member="DAC_TypeDef::DHR12L2" ref="a2e45f9c9d67e384187b25334ba0a3e3d" args="" -->
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<p>DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 </p>

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<p>DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 </p>

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<p>DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 </p>

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<a class="anchor" id="a804c7e15dbb587c7ea25511f6a7809f7"></a><!-- doxytag: member="DAC_TypeDef::DHR12R2" ref="a804c7e15dbb587c7ea25511f6a7809f7" args="" -->
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<p>DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 </p>

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<a class="anchor" id="a1590b77e57f17e75193da259da72095e"></a><!-- doxytag: member="DAC_TypeDef::DHR12RD" ref="a1590b77e57f17e75193da259da72095e" args="" -->
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<p>Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 </p>

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<p>DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 </p>

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<p>DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C </p>

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<p>DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 </p>

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<a class="anchor" id="aa710505be03a41981c35bacc7ce20746"></a><!-- doxytag: member="DAC_TypeDef::DOR1" ref="aa710505be03a41981c35bacc7ce20746" args="" -->
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<p>DAC channel1 data output register, Address offset: 0x2C </p>

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<a class="anchor" id="aba9fb810b0cf6cbc1280c5c63be2418b"></a><!-- doxytag: member="DAC_TypeDef::DOR2" ref="aba9fb810b0cf6cbc1280c5c63be2418b" args="" -->
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<p>DAC channel2 data output register, Address offset: 0x30 </p>

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<a class="anchor" id="af6aca2bbd40c0fb6df7c3aebe224a360"></a><!-- doxytag: member="DAC_TypeDef::SR" ref="af6aca2bbd40c0fb6df7c3aebe224a360" args="" -->
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<p>DAC status register, Address offset: 0x34 </p>

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<a class="anchor" id="a896bbb7153af0b67ad772360feaceeb4"></a><!-- doxytag: member="DAC_TypeDef::SWTRIGR" ref="a896bbb7153af0b67ad772360feaceeb4" args="" -->
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<p>DAC software trigger register, Address offset: 0x04 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>D:/123/stm32f4_blink_led-1.2.2-120323/inc/<a class="el" href="stm32f4xx_8h_source.html">stm32f4xx.h</a></li>
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